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2.5v or 3.3v, 200-mhz, 12-output zero delay buffe r cy29772 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07572 rev. *a revised september 1, 2005 features ? output frequency range: 8.33 mhz to 200 mhz ? input frequency range: 6.25 mhz to 125 mhz ? 2.5v or 3.3v operation ? split 2.5v/3.3v outputs ? 2% max. output duty cycle variation ? 7 ps rms typical cycle-to-cycle jitter ? 6 ps rms typical period jitter ? 12 clock outputs: drive up to 24 clock lines ? one feedback output ? three reference clock inputs: crystal or lvcmos ? 300 ps max. output-output skew ? phase-locked loop (pll) bypass mode ? spread aware? ? output enable/disable ? pin-compatible with mpc9772 and mpc972 ? industrial temperature range: ?40c to +85c ? 52-pin 1.0-mm tqfp package description the cy29772 is a low-voltage high-performance 200-mhz pll-based zero delay buffer designed for high-speed clock-distribution applications. the cy29772 features one on-chip crystal oscillator and two lvcmos reference clock inputs and provides 12 outputs parti- tioned in three banks of four outputs each. each bank divides the vco output per sel(a:c) settings, see functional table . these dividers allow output to input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. each lvcmos-compatible output can drive 50 ? series- or parallel-terminated transmission lines. for series-terminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of 1:24. the pll is ensured stable given that the vco is configured to run between 200 mhz to 500 mhz. this allows a wide range of output frequencies from 8 mhz to 200 mhz. for normal operation, the external feedback input, fb_in, is connected to the feedback output, fb_out. the internal vco is running at multiples of the input reference clock set by the feedback divider, see frequency table. when pll_en is low, pll is bypassed and the reference clock directly feeds the output dividers. this mode is fully static and the minimum input clock frequency specification does not apply. block diagram pin configuration avss mr#/oe sclk sda ta fb_sel2 pll_en ref_sel tclk_sel tclk0 tclk1 xin xout avdd fb_sel1 sync vss qc0 vddqc qc1 selc0 selc1 qc2 vddqc qc3 vss inv_clk selb1 selb0 sela1 sela0 qa3 vddqa qa2 vss qa1 vddqa qa0 vss vco_sel vss qb0 v ddqb qb1 vss qb2 v ddqb qb3 fb_in vss fb_out vdd fb_sel0 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 cy29772 ref_sel 0 1 0 1 phase detector vco lpf sync frz d q qa0 sync frz d q sync frz d q sync frz d q sync frz d q sync frz d q 0 1 /2 power-on reset output disable circuitry data generator /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 sync pulse xin xout tclk0 tclk1 tclk_sel fb_in fb_sel2 mr#/oe sela(0,1) 2 selb(0,1) 2 selc(0,1) 2 fb_sel(0,1) 2 sclk sdata inv_clk qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 fb_out sync 12 vco_sel pll_en
cy29772 document #: 38-07572 rev. *a page 2 of 12 pin description [1] pin name i/o type description 11 xin i analog crystal oscillator input . 12 xout o analog crystal oscillator output . 9 tclk0 i, pu lvcmos lvcmos/lvttl reference clock input . 10 tclk1 i, pu lvcmos lvcmos/lvttl reference clock input . 44, 46, 48, 50 qa(3:0) o lvcmos clock output bank a . 32, 34, 36, 38 qb(3:0) o lvcmos clock output bank b . 16, 18, 21, 23 qc(3:0) o lvcmos clock output bank c . 29 fb_out o lvcmos feedback clock output . connect to fb_in for normal operation. 31 fb_in i, pu lvcmos feedback clock input . connect to fb_out for normal operation. this input should be at the same voltage rail as input reference clock. see table 1 . 25 sync o lvcmos synchronous pulse output . this output is us ed for system synchro- nization. 6 pll_en i, pu lvcmos pll enable/bypass input . when low, pll is disabled/bypassed. and the input clock connects to the output dividers. 2 mr#/oe i, pu lvcmos master reset and output enable/disable input . see table 2 . 8 tclk_sel i, pu lvcmos lvcmos clock reference select input . see table 2 . 7 ref_sel i, pu lvcmos lvcmos/lvpecl reference select input . see table 2 . 52 vco_sel i, pu lvcmos vco operating frequency select input . see table 2 . 14 inv_clk i, pu lvcmos qc(2,3) phase selection input . see table 2 . 5, 26, 27 fb_sel(2:0) i, pu lvcmos feedback divider select input . see ta ble 6 . 42, 43 sela(1,0) i, pu lvcmos frequency select input, bank a . see ta ble 3 . 40, 41 selb(1,0) i, pu lvcmos frequency select input, bank b . see ta ble 4 . 19, 20 selc(1,0) i, pu lvcmos frequency select input, bank c . see ta ble 5 . 3 sclk i, pu lvcmos serial clock input . 4 sdata i, pu lvcmos serial data input . 45, 49 vddqa supply vdd 2.5v or 3.3v power supply for bank a output clocks . [2,3] 33, 37 vddqb supply vdd 2.5v or 3.3v power supply for bank b output clocks . [2,3] 22, 17 vddqc supply vdd 2.5v or 3.3v power supply for bank c output clocks . [2,3] 13 avdd supply vdd 2.5v or 3.3v power supply for pll . [2,3] 28 vdd supply vdd 2.5v or 3.3v power supply for core and inputs . [2,3] 1 avss supply ground analog ground . 15, 24, 30, 35, 39, 47, 51 vss supply ground common ground . notes: 1. pu = internal pull-up, pd = internal pull-down. 2. a 0.1- f bypass capacitor should be placed as close as possible to each positive power pin (<0.2?). if these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be canc elled by the lead inductance of the traces. 3. avdd and vdd pins must be connected to a power supply level th at is at least equal or higher than that of vddqa, vddqb, and v ddqc power supply pins.
cy29772 document #: 38-07572 rev. *a page 3 of 12 table 1. frequency table feedback output divider vco input frequency range (avdd = 3.3v) input frequency range (avdd = 2.5v) 4 input clock * 4 50 mhz to 125 mhz 50 mhz to 95 mhz 6 input clock * 6 33.3 mhz to 83.3 mhz 33.3 mhz to 63.3 mhz 8 input clock * 8 25 mhz to 62.5 mhz 25 mhz to 47.5 mhz 10 input clock * 10 20 mhz to 50 mhz 20 mhz to 38 mhz 12 input clock * 12 16.6 mhz to 41.6 mhz 16.6 mhz to 31.6 mhz 16 input clock * 16 12.5 mhz to 31.25 mhz 12.5 mhz to 23.75 mhz 20 input clock * 20 10 mhz to 25 mhz 10 mhz to 19 mhz 24 input clock * 24 8.3 mhz to 20.8 mhz 8.3 mhz to 15.8 mhz 32 input clock * 32 6.25 mhz to 15.625 mhz 6.25 mhz to 11.8 mhz 40 input clock * 40 5 mhz to 12.5 mhz 5 mhz to 9.5mhz table 2. function table (configuration controls) control default 0 1 ref_sel 1 tclk0, tclk1 crystal oscillator tclk_sel 1 tclk0 tclk1 vco_sel 1 vco 2 (low input frequency range) vco 1 (high input frequency range) pll_en 1 bypass mode, pll disabled. the input clock connects to the output dividers pll enabled. the vco output connects to the output dividers inv_clk 1 qc2 and qc3 are in phase with qc0 and qc1 qc2 and qc3 are inverted (180 phase shift) with respect to qc0 and qc1 mr#/oe 1 outputs disabled (three-state ) and reset of the device. during reset/output disable the pll feedback loop is open and the vco running at its minimum frequency. the device is reset by the internal power-on re set (por) circuitry during power-up. outputs enabled table 3. function table (bank a) vco_sel sela1 sela0 qa(0:3) 000 8 001 12 010 16 011 24 100 4 101 6 110 8 111 12 table 4. function table (bank b) vco_sel selb1 selb0 qb(0:3) 000 8 001 12 010 16 011 20 100 4 101 6 110 8 111 10 table 5. function table (bank c) vco_sel selc1 selc0 qc(0:3) 000 4 001 8 010 12 011316 100 2 101 4 110 6 111 8
cy29772 document #: 38-07572 rev. *a page 4 of 12 table 6. function table (fb_out) vco_sel fb_sel2 fb_sel1 fb_sel0 fb_out 0000 8 0001 12 0010 16 0011 20 0100 16 0101 24 0110 32 0111 40 1000 4 1001 6 1010 8 1011 10 1100 8 1101 12 1110 16 1111 20
cy29772 document #: 38-07572 rev. *a page 5 of 12 absolute maximum conditions parameter description condition min. max. unit v dd dc supply voltage ?0.3 5.5 v v dd dc operating voltage functional 2.375 3.465 v v in dc input voltage relative to v ss ?0.3 v dd + 0.3 v v out dc output voltage relative to v ss ?0.3 v dd + 0.3 v v tt output termination voltage ? v dd 2v lu latch-up immunity functional 200 ? ma r ps power supply ripple ripple frequency < 100 khz ? 150 mvp-p t s temperature, storage non-functional ?65 +150 c t a temperature, operating ambient functional ?40 +85 c t j temperature, junction functional ? +150 c ? jc dissipation, junction to case functional ? 23 c/w ? ja dissipation, junction to ambient functional ? 55 c/w esd h esd protection (human body model) 2000 ? v fit failure in time manufacturing test 10 ppm dc electrical specifications (v dd = 2.5v 5%, t a = ?40c to +85c) parameter description condition min. typ. max. unit v il input voltage, low lvcmos ? ? 0.7 v v ih input voltage, high lvcmos 1.7 ? v dd +0.3 v v ol output voltage, low [4] i ol = 15 ma ? ? 0.6 v v oh output voltage, high [4] i oh = ?15 ma 1.8 ? ? v i il input current, low [5] v il = v ss ? ? ?100 a i ih input current, high [5] v il = v dd ??100 a i dda pll supply current avdd only ? 5 10 ma i ddq quiescent supply current all vdd pins except avdd ? ? 8 ma i dd dynamic supply current outputs loaded @ 100 mhz ? 135 ? ma c in input pin capacitance ? 4 ? pf z out output impedance 14 18 22 ? dc electrical specifications (v dd = 3.3v 5%, t a = ?40c to +85c) parameter description condition min. typ. max. unit v il input voltage, low lvcmos ? ? 0.8 v v ih input voltage, high lvcmos 2.0 ? v dd + 0.3 v v ol output voltage, low [4] i ol = 24 ma ? ? 0.55 v i ol = 12 ma ? ? 0.30 v oh output voltage, high [4] i oh = ?24 ma 2.4 ? ? v i il input current, low [5] v il = v ss ? ? ?100 a i ih input current, high [5] v il = v dd ??100 a i dda pll supply current avdd only ? 5 10 ma i ddq quiescent supply current all vdd pins except avdd ? ? 8 ma i dd dynamic supply current outputs loaded @ 100 mhz ? 225 ? ma c in input pin capacitance ? 4 ? pf z out output impedance 12 15 18 ? notes: 4. driving one 50 ? parallel-terminated transmission line to a termination voltage of v tt . alternatively, each output drives up to two 50 ? series-terminated transmis- sion lines. 5. inputs have pull-up or pull-down resistors that affect the input current.
cy29772 document #: 38-07572 rev. *a page 6 of 12 ac electrical specifications (v dd = 2.5v 5%, t a = ?40c to +85c) [6] parameter description condition min. typ. max. unit f vco vco frequency 200 ? 380 mhz f xtal crystal frequency range see table 7 10 ? 25 mhz f in input frequency 4 feedback 50 ? 95 mhz 6 feedback 33.3 ? 63.3 8 feedback 25 ? 47.5 10 feedback 20 ? 38 12 feedback 16.6 ? 31.6 16 feedback 12.5 ? 23.75 20 feedback 10 ? 19 24 feedback 8.3 ? 15.8 32 feedback 6.25 ? 11.8 40 feedback 5 ? 9.5 bypass mode (pll_en = 0) 0 ? 200 f refdc input duty cycle 25 ? 75 % t r , t f tclk input rise/falltime 0.7v to 1.7v ? ? 1.0 ns f max maximum output frequency 2 output 100 ? 190 mhz 4 output 50 ? 95 6 output 33.3 ? 63.3 8 output 25 ? 47.5 10 output 20 ? 38 12 output 16.6 ? 31.6 16 output 12.5 ? 23.75 20 output 10 ? 19 24 output 8.3 ? 15.8 f sclk serial clock frequency ? ? 20 mhz dc output duty cycle f max < 100 mhz 47.5 ? 52.5 % f max > 100 mhz 45 ? 55 t r , t f output rise/fall times 0 .6v to 1.8v 0.1 ? 1.0 ns t ( ) propagation delay (static phase offset) tclk to fb_in ?125 ? 125 ps t sk(o) output-to-output skew skew within bank a ? ? 75 ps skew within bank b ? ? 100 skew within bank c ? ? 150 t sk(b) bank-to-bank skew ? ? 400 ps t plz, hz output disable time ? ? 10 ns t pzl, zh output enable time ? ? 10 ns bw pll closed loop bandwidth (?3 db) 4 feedback ? 1.3?2.0 ? mhz 6 feedback ? 0.7?1.3 ? 8 feedback ? 0.9?1.3 ? 10 feedback ? 0.6?1.1 ? 12 feedback ? 0.6?0.9 ? 16 feedback ? 0.4?0.6 ? 20 feedback ? 0.6?0.9 ? note: 6. ac characteristics apply for parallel output termination of 50 ? to v tt . outputs are at same supply voltage unless otherwise stated. parameters are guaranteed by characterization and are not 100% tested.
cy29772 document #: 38-07572 rev. *a page 7 of 12 t jit(cc) cycle-to-cycle jitter same frequency (125 mhz) rms (1 ) ?7 30ps same frequency ? ? 150 multiple frequencies ? ? 435 t jit(per) period jitter same frequency (125 mhz) rms (1 ) ?6 30ps same frequency ? 45 75 multiple frequencies ? ? 235 t jit( ) i/o phase jitter ? ? 150 ps t lock maximum pll lock time ? ? 1 ms ac parameters (v dd = 3.3v 5%, t a = ?40c to +85c) [6] parameter description condition min. typ. max. unit f vco vco frequency 200 ? 500 mhz f xtal crystal frequency range see table 7 10 ? 25 mhz f in input frequency 4 feedback 50 ? 125 mhz 6 feedback 33.3 ? 83.3 8 feedback 25 ? 62.5 10 feedback 20 ? 50 12 feedback 16.6 ? 41.6 16 feedback 12.5 ? 31.25 20 feedback 10 ? 25 24 feedback 8.3 ? 20.8 32 feedback 6.25 ? 15.625 40 feedback 5 ? 12.5 bypass mode (pll_en = 0) 0 ? 200 f refdc input duty cycle 25 ? 75 % t r , t f tclk input rise/falltime 0.8v to 2.0v ? ? 1.0 ns f max maximum output frequency 2 output 100 ? 200 mhz 4 output 50 ? 125 6 output 33.3 ? 83.3 8 output 25 ? 62.5 10 output 20 ? 50 f max maximum output frequency (continued) 12 output 16.6 ? 41.6 mhz 16 output 12.5 ? 31.25 20 output 10 ? 25 24 output 8.3 ? 20.8 f sclk serial clock frequency ? ? 20 mhz dc output duty cycle f max < 100 mhz 48 ? 52 % f max > 100 mhz 45 ? 55 t r , t f output rise/fall times 0.55v to 2.4v 0.1 ? 1.0 ns t ( ) propagation delay (static phase offset) tclk to fb_in, same vdd ?125 ? 125 ps t sk(o) output-to-output skew sk ew within bank a ? ? 75 ps skew within bank b ? ? 100 ac electrical specifications (v dd = 2.5v 5%, t a = ?40c to +85c) (continued) [6] parameter description condition min. typ. max. unit
cy29772 document #: 38-07572 rev. *a page 8 of 12 sync output in situations where output frequency relationships are not integer multiples of each other the sync output provides a signal for system synchronization. the cy29772 monitors the relationship between the qa and the qc out put clocks. it provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the qa and qc outputs. the duration and the placement of the pulse depend on the higher of the qa and qc output frequencies. figure 1 illus- trates various waveforms for t he sync output. note that the sync output is defined for all possible combinations of the qa and qc outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. skew within bank c ? ? 150 tsk(b) bank-to-bank skew ? ? 325 ps t plz, hz output disable time ? ? 8 ns t pzl, zh output enable time ? ? 8 ns bw pll closed-loop bandwidth (?3 db) 4 feedback ? 1.3?2.0 ? mhz 6 feedback ? 0.7?1.3 ? 8 feedback ? 0.9?1.3 ? 10 feedback ? 0.6?1.1 ? 12 feedback ? 0.6?0.9 ? 16 feedback ? 0.?0.6 ? 20 feedback ? 0.6?0.9 ? t jit(cc) cycle-to-cycle jitter same frequency (125 mhz) rms (1 ) ?730ps same frequency ? ? 100 multiple frequencies ? ? 375 t jit(per) period jitter same frequency (125 mhz) rms (1 ) ?630ps same frequency ? 45 75 multiple frequencies ? ? 225 t jit( ) i/o phase jitter i/o same vdd ? ? 150 ps t lock maximum pll lock time ? ? 1 ms ac parameters (v dd = 3.3v 5%, t a = ?40c to +85c) (continued) [6] parameter description condition min. typ. max. unit
cy29772 document #: 38-07572 rev. *a page 9 of 12 power management the individual output enable/freeze control of the cy29772 allows the user to implement unique power management schemes into the design. the outputs are stopped in the logic ?0? state when the freeze contro l bits are activated. the serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. the qc0 and fb_out outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the loading of the serial data. an output is frozen when a logic ?0? is programmed and enabled when a logic ?1? is written. the enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of pa rtial ?runt? clocks. the serial input register is programmed through the sdata input by writing a logic ?0? start bit followed by 12 nrz freeze enable bits. the period of each sdata bit equals the period of the free running sclk signal. the sdata is sampled on the rising edge of sclk. sync qc qa sync qc qa sync qa qc sync qc qa sync qa qc sync qc qa sync qc qa vco 1:1 mode 2:1 mode 3:1 mode 3:2 mode 4:1 mode 4:3 mode 6:1 mode figure 1.
cy29772 document #: 38-07572 rev. *a page 10 of 12 table 7. suggested oscillator crystal parameters parameter description conditions min. typ. max. unit t c frequency tolerance ? ? 1100 ppm t s frequency temperature stability (t a ?10 to +60c) ? ? 100 ppm t a aging (first three years @ 25c) ? ? 5 ppm/yr c l load capacitance the crystal?s rated load ? 20 ? pf r esr effective series resistance (esr) ? 40 80 ohm d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0-d3 are the control bits for qa0-qa3, respectively d4-d7 are the control bits for qb0-qb3, respectively d8-d10 are the control bits for qc1-qc3, respectively d11 is the control bit for sync start bit figure 2. pulse generator z = 50 ohm zo = 50 ohm vtt zo = 50 ohm vtt r t = 50 ohm r t = 50 ohm figure 3. lvcmos_clk ac test reference for v dd = 3.3v/2.5v t( ) lvcmos_clk fb_in vdd gnd vdd/2 vdd gnd vdd/2 figure 4. lvcmos propagation delay t( ), static phase offset vdd gnd vdd/2 t p t0 dc = tp / t0 x 100% figure 5. output duty cycle (dc)
cy29772 document #: 38-07572 rev. *a page 11 of 12 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimension spread aware is a trademark of cypress semiconductor. all product and company na mes mentioned in this document are the trademarks of their respective holders. t sk(o) vdd gnd vdd/2 vdd gnd vdd/2 figure 6. outpu t-to-output skew, t sk(o) ordering information part number package type product flow cy29772ai 52-pin tqfp industrial, ?40 c to +85 c cy29772ait 52-pin tqfp ? tape and reel industrial,?40 c to 85 c lead-free cy29772axi 52-pin tqfp industrial, ?40 c to +85 c CY29772AXIT 52-pin tqfp ? tape and reel industrial,?40 c to 85 c 52-lead thin plastic quad flat pack (10 x 10 x 1.0 mm) a52b 51-85158-**
cy29772 document #: 38-07572 rev. *a page 12 of 12 document history page document title:cy29772 2.5v or 3.3v, 200-mhz, 12-output zero delay buffer document number: 38-07572 rev. ecn no. issue date orig. of change description of change ** 129007 09/03/03 rgl new data sheet *a 395853 see ecn rgl added lead-free devices added jitter typical specs in the features section

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